(1) Field of the Invention
The invention relates to the method of fabrication of integrated circuit devices, and more particularly, to a method of forming a sub-quarter-micron MOSFET structure with a raised source and drain in the fabrication of integrated circuits.
(2) Description of the Prior Art
In sub-quarter-micron MOSFET architecture, it is necessary to use ultra-shallow source and drain regions. Low energy ion implantation is typically used to form such regions.
For example, FIG. 1 illustrates a semiconductor substrate 10, preferably composed of monocrystalline silicon. A layer of silicon oxide 12 is formed on the surface of the substrate. A polysilicon layer is deposited and patterned to form gate electrode 16. A typical LDD (lightly doped source and drain) structure is formed by an LDD mask implant followed by spacer oxide deposition and etching and then a source/drain mask implant. Lightly doped source and drain regions 20 are shown in FIG. 1.
U.S. Pat. No. 5,200,352 to Pfiester teaches a method of forming a MOSFET device using raised epitaxial regions adjacent to lightly doped substrate source/drain regions allowing precise control of the source/drain region doping profiles. U.S. Pat. No. 5,447,874 to Grivna et al teaches a method of forming an MOSFET device using a dual metal gate formed in an oxide opening. Using a chemical mechanical polishing step to planarize the surface eliminates the problems encountered in etching different metals. U.S. Pat. No. 5,856,225 to Lee et al teaches of forming an MOSFET device where the source/drain regions are built prior to the implantation of the channel region under the gate. This allows more precise control of the source/drain positions, thereby controlling the electrical parameters of the MOSFET device.